Is your memory hierarchy stopping your microprocessor from performing at the high level it should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem. The book tells you everything you need to know about the logical design and operation, physical design and operation, performance characteristics and resulting design trade-offs, and the energy consumption of modern memory hierarchies. You learn how to to tackle the challenging optimization problems that result from the side-effects that can appear at any point in the entire hierarchy. As a result you will be able to design and emulate the entire memory hierarchy.
- Understand all levels of the system hierarchy -Xcache, DRAM, and disk.
- Evaluate the system-level effects of all design choices.
- Model performance and energy consumption for each component in the memory hierarchy.
Inhaltsverzeichnis
1;Front Cover;1 2;In Praise of Memory Systems: Cache, DRAM, Disk;2 3;Memory Systems Cache, DRAM, Disk;6 4;Copyright Page;7 5;Contents;10 6;Preface;32 7;Overview. On Memory Systems and Their Design;36 7.1;Ov.1 Memory Systems;37 7.2;Ov.2 Four Anecdotes on Modular Design;49 7.3;Ov.3 Cross-Cutting Issues;55 7.4;Ov.4 An Example Holistic Analysis;76 7.5;Ov.5 What to Expect;89 8;Part I. Cache;90 8.1;Chapter 1. An Overview of Cache Principles;92 8.1.1;1.1 Caches, Caches, and Caches;94 8.1.2;1.2 Locality Principles;97 8.1.3;1.3 What to Cache, Where to Put It, and How to Maintain It;101 8.1.4;1.4 Insights and Optimizations;108 8.2;Chapter 2. Logical Organization;114 8.2.1;2.1 Logical Organization: A Taxonomy;114 8.2.2;2.2 Transparently Addressed Caches;117 8.2.3;2.3 Non-Transparently Addressed Caches;125 8.2.4;2.4 Virtual Addressing and Protection;127 8.2.5;2.5 Distributed and Partitioned Caches;132 8.2.6;2.6 Case Studies;138 8.3;Chapter 3. Management of Cache Contents;152 8.3.1;3.1 Case Studies: On-Line Heuristics;155 8.3.2;3.2 Case Studies: Off-Line Heuristics;186 8.3.3;3.3 Case Studies: Combined Approaches;204 8.3.4;3.4 Discussions;237 8.3.5;3.5 Building a Content-Management;247 8.4;Chapter 4. Management of Cache Consistency;252 8.4.1;4.1 Consistency with Backing Store;253 8.4.2;4.2 Consistency with Self;255 8.4.3;4.3 Consistency with Other Clients;261 8.5;Chapter 5. Implementation Issues;292 8.5.1;5.1 Overview;292 8.5.2;5.2 SRAM Implementation;293 8.5.3;5.3 Advanced SRAM Topics;328 8.5.4;5.4 Cache Implementation;332 8.6;Chapter 6. Cache Case Studies;336 8.6.1;6.1 Logical Organization;336 8.6.2;6.2 Pipeline Interface;339 8.6.3;6.3 Case Studies of Detailed Itanium-2 Circuits;340 9;Part II. DRAM;348 9.1;Chapter 7. Overview of DRAMs;350 9.1.1;7.1 DRAM Basics: Internals, Operation;351 9.1.2;7.2 Evolution of the DRAM Architecture;357 9.1.3;7.3 Modern-Day DRAM Standards;367 9.1.4;7.4 Fully Buffered DIMM: A Compromise of Sorts;383 9.1.5;7.5 Issues in DRAM Systems, Briefly;386 9.2
;Chapter 8. DRAM Device Organization: Basic Circuits and Architecture;388 9.2.1;8.1 DRAM Device Organization;388 9.2.2;8.2 DRAM Storage Cells;390 9.2.3;8.3 RAM Array Structures;393 9.2.4;8.4 Differential Sense Amplifier;395 9.2.5;8.5 Decoders and Redundancy;401 9.2.6;8.6 DRAM Device Control Logic;403 9.2.7;8.7 DRAM Device Confi guration;405 9.2.8;8.8 Data I/O;407 9.2.9;8.9 DRAM Device Packaging;408 9.2.10;8.10 DRAM Process Technology and Process Scaling Considerations;409 9.3;Chapter 9. DRAM System Signaling and Timing;412 9.3.1;9.1 Signaling System;412 9.3.2;9.2 Transmission Lines on PCBs;414 9.3.3;9.3 Termination;428 9.3.4;9.4 Signaling;430 9.3.5;9.5 Timing Synchronization;434 9.3.6;9.6 Selected DRAM Signaling and Timing Issues;437 9.3.7;9.7 Summary;443 9.4;Chapter 10. DRAM Memory System Organization;444 9.4.1;10.1 Conventional Memory System;444 9.4.2;10.2 Basic Nomenclature;444 9.4.3;10.3 Memory Modules;452 9.4.4;10.4 Memory System Topology;457 9.4.5;10.5 Summary;458 9.5;Chapter 11. Basic DRAM Memory-Access Protocol;460 9.5.1;11.1 Basic DRAM Commands;460 9.5.2;11.2 DRAM Command Interactions;471 9.5.3;11.3 Additional Constraints;485 9.5.4;11.4 Command Timing Summary;489 9.5.5;11.5 Summary;489 9.6;Chapter 12. Evolutionary Developments of DRAM Device Architecture;492 9.6.1;12.1 DRAM Device Families;492 9.6.2;12.2 Historical-Commodity DRAM Devices;493 9.6.3;12.3 Modern-Commodity DRAM Devices;499 9.6.4;12.4 High Bandwidth Path;515 9.6.5;12.5 Low Latency;529 9.6.6;12.6 Interesting Alternatives;530 9.7;Chapter 13. DRAM Memory Controller;532 9.7.1;13.1 DRAM Controller Architecture;532 9.7.2;13.2 Row-Buffer-Management Policy;534 9.7.3;13.3 Address Mapping (Translation);537 9.7.4;13.4 Performance Optimization;546 9.7.5;13.5 Summary;553 9.8;Chapter 14. The Fully Buffered DIMM Memory System;554 9.8.1;14.1 Introduction;554 9.8.2;14.2 Architecture;556 9.8.3;14.3 Signaling and Timing;559 9.8.4;14.4 Access Protocol;561 9.8.5;14.5 The Advanced Memory Buffer;565 9.8.6;14.6 Reliabi
lity, Availability, and Serviceability;567 9.8.7;14.7 FB-DIMM Performance Characteristics;570 9.8.8;14.8 Perspective;575 9.9;Chapter 15. Memory System Design Analysis;576 9.9.1;15.1 Overview;576 9.9.2;15.2 Workload Characteristics;578 9.9.3;15.3 The RAD Analytical Framework;586 9.9.4;15.4 Simulation-Based Analysis;605 9.9.5;15.5 A Latency-Oriented Study;625 9.9.6;15.6 Concluding Remarks;631 10;Part III. Disk;634 10.1;Chapter 16. Overview of Disks;636 10.1.1;16.1 History of Disk Drives;636 10.1.2;16.2 Principles of Hard Disk Drives;641 10.1.3;16.3 Classifications of Disk Drives;644 10.1.4;16.4 Disk Performance Overview;645 10.1.5;16.5 Future Directions in Disks;647 10.2;Chapter 17. The Physical Layer;650 10.2.1;17.1 Magnetic Recording;650 10.2.2;17.2 Mechanical and Magnetic Components;655 10.2.3;17.3 Electronics;675 10.3;Chapter 18. The Data Layer;684 10.3.1;18.1 Disk Blocks and Sectors;684 10.3.2;18.2 Tracks and Cylinders;687 10.3.3;18.3 Address Mapping;689 10.3.4;18.4 Zoned-Bit Recording;693 10.3.5;18.5 Servo;697 10.3.6;18.6 Sector ID and No-ID Formatting;705 10.3.7;18.7 Capacity;707 10.3.8;18.8 Data Rate;708 10.3.9;18.9 Defect Management;708 10.4;Chapter 19. Performance Issues and Design Trade-Offs;712 10.4.1;19.1 Anatomy of an I/O;712 10.4.2;19.2 Some Basic Principles;716 10.4.3;19.3 BPI vs. TPI;723 10.4.4;19.4 Effect of Drive Capacity;724 10.4.5;19.5 Concentric Tracks vs. Spiral Track;727 10.4.6;19.6 Average Seek;729 10.5;Chapter 20. Drive Interface;734 10.5.1;20.1 Overview of Interfaces;734 10.5.2;20.2 ATA;737 10.5.3;20.3 Serial ATA;738 10.5.4;20.4 SCSI;740 10.5.5;20.5 Serial SCSI;741 10.5.6;20.6 Fibre Channel;742 10.5.7;20.7 Cost, Performance, and Reliability;744 10.6;Chapter 21. Operational Performance Improvement;746 10.6.1;21.1 Latency Reduction Techniques;746 10.6.2;21.2 Command Queueing andScheduling;750 10.6.3;21.3 Reorganizing Data on the Disk;758 10.6.4;21.4 Handling Writes;762 10.6.5;21.5 Data Compression;764 10.7;Chapter 22. The Cache Layer;766 10.7.
1;22.1 Disk Cache;766 10.7.2;22.2 Cache Organizations;770 10.7.3;22.3 Caching Algorithms;776 10.8;Chapter 23. Performance Testing;782 10.8.1;23.1 Test and Measurement;782 10.8.2;23.2 Basic Tests;785 10.8.3;23.3 Benchmark Tests;790 10.8.4;23.4 Drive Parameters Tests;792 10.9;Chapter 24. Storage Subsystems;798 10.9.1;24.1 Data Striping;798 10.9.2;24.2 Data Mirroring;800 10.9.3;24.3 RAID;805 10.9.4;24.4 SAN;815 10.9.5;24.5 NAS;817 10.9.6;24.6 iSCSI;818 10.10;Chapter 25. Advanced Topics;820 10.10.1;25.1 Perpendicular Recording;820 10.10.2;25.2 Patterned Media;823 10.10.3;25.3 Thermally Assisted Recording;825 10.10.4;25.4 Dual Stage Actuator;827 10.10.5;25.5 Adaptive Formatting;829 10.10.6;25.6 Hybrid Disk Drive;831 10.10.7;25.7 Object-Based Storage;833 10.11;Chapter 26. Case Study;838 10.11.1;26.1 The Mechanical Components;838 10.11.2;26.2 Electronics;841 10.11.3;26.3 Data Layout;841 10.11.4;26.4 Interface;844 10.11.5;26.5 Cache;845 10.11.6;26.6 Performance Testing;845 11;Part IV. Cross-Cutting Issues;848 11.1;Chapter 27. The Case for Holistic Design;850 11.1.1;27.1 Anecdotes, Revisited;851 11.1.2;27.2 Perspective;862 11.2;Chapter 28. Analysis of Cost and Performance;864 11.2.1;28.1 Combining Cost and Performance;864 11.2.2;28.2 Pareto Optimality;865 11.2.3;28.3 Taking Sampled Averages Correctly;868 11.2.4;28.4 Metrics for Computer Performance;873 11.2.5;28.5 Analytical Modeling and the Miss-Rate Function;878 11.3;Chapter 29. Power and Leakage;882 11.3.1;29.1 Sources of Leakage in CMOS Devices;882 11.3.2;29.2 A Closer Look at Subthreshold Leakage;886 11.3.3;29.3 CACTI and Energy/Power Breakdown of Pipelined Nanometer Caches;890 11.4;Chapter 30. Memory Errors and Error Correction;900 11.4.1;30.1 Types and Causes of Failures;900 11.4.2;30.2 Soft Error Rates and Trends;903 11.4.3;30.3 Error Detection and Correction;904 11.4.4;30.4 Reliability of Non-DRAM Systems;915 11.4.5;30.5 Space Shuttle Memory System;916 11.5;Chapter 31. Virtual Memory;918 11.5.1;31.1 A Virtual Memory
Primer;919 11.5.2;31.2 Implementing Virtual Memory;941 12;References;956 13;Index;990
