Efficient design of embedded processors plays a critical role in embedded systems design. Processor description languages and their associated specification, exploration and rapid prototyping methodologies are used to find the best possible design for a given set of applications under various design constraints, such as area, power and performance. This book is the first, comprehensive survey of modern architecture description languages and will be an invaluable reference for embedded system architects, designers, developers, and validation engineers. Readers will see that the use of particular architecture description languages will lead to productivity gains in designing particular (application-specific) types of embedded processors.
- Comprehensive coverage of all modern architecture description languages. . . use the right ADL to design your processor to fit your application
- Most up-to-date information available about each architecture description language from the developers. . . save time chasing down reliable documentation
- Describes how each architecture desccription language enables key design automation tasks, such as simulation, synthesis and testing. . . fit the ADL to your design cycle
Inhaltsverzeichnis
1;Front Cover;1 2;Processor Description Languages Applications ;4 3;Copyright Page;5 4;Table of Contents;8 5;List of Contributors;18 6;Preface;26 7;About the Editors;28 8;Chapter 1. Introduction to Architecture Description Languages;30 8.1;1.1 What is an Architecture Description Language?;31 8.2;1.2 ADLs and Other Languages;32 8.3;1.3 Classification of Contemporary ADLs;33 8.3.1;1.3.1 Content-based Classification of ADLs;34 8.3.2;1.3.2 Objective-based Classification of ADLs;35 8.4;1.4 ADLs: Past, Present, and Future;37 8.5;1.5 Book Organization;38 8.6;References;39 9;Chapter 2. ADL-driven Methodologies for Design Automation of Embedded Processors;42 9.1;2.1 Design Space Exploration;42 9.2;2.2 Retargetable Compiler Generation;43 9.2.1;2.2.1 Retargetability Based on ADL Content;45 9.2.2;2.2.2 Retargetability Based on Compiler Phases;46 9.2.3;2.2.3 Retargetability Based on Architectural Abstractions;47 9.3;2.3 Retargetable Simulator Generation;50 9.3.1;2.3.1 Interpretive Simulation;51 9.3.2;2.3.2 Compiled Simulation;51 9.3.3;2.3.3 Mixed Approaches;51 9.4;2.4 Architecture Synthesis;52 9.4.1;2.4.1 Implementation Generation Using Processor Templates;52 9.4.2;2.4.2 ADL-driven Implementation Generation;53 9.5;2.5 Top-Down Validation;53 9.5.1;2.5.1 Validation of ADL Specification;54 9.5.2;2.5.2 Implementation Validation;56 9.6;2.6 Conclusions;59 9.7;References;59 10;Chapter 3. MIMOLAA Fully Synthesizable Language;64 10.1;3.1 Introduction;64 10.1.1;3.1.1 Origin of the Language;64 10.1.2;3.1.2 Purpose of the Language;65 10.1.3;3.1.3 Related Work: State of the Art in the Early Years;67 10.1.4;3.1.4 Outline of This Chapter;68 10.2;3.2 Salient Features of the Mimola Language;68 10.2.1;3.2.1 Overall Structure of Description;68 10.2.2;3.2.2 Declarations, Data Types, and Operations;68 10.2.3;3.2.3 Program Definition;69 10.2.4;3.2.4 Structure Definition;72 10.2.5;3.2.5 Linking Behavior and Structure;75 10.2.6;3.2.6 Putting Things Together;77 10.3;3.3 Tools and Results;77 10.3.1;3.3.1
Design Flow;77 10.3.2;3.3.2 The Front-end and Internal Design Representations;77 10.3.3;3.3.3 Mapping to Register Transfers;78 10.3.4;3.3.4 Simulation;78 10.3.5;3.3.5 Architectural Synthesis;79 10.3.6;3.3.6 Test Program Generation;83 10.3.7;3.3.7 Code Generation;85 10.3.8;3.3.8 Overall View of the Dependence among MSS Tools;86 10.3.9;3.3.9 Designs Using MSS2;87 10.4;3.4 Conclusions;88 10.4.1;3.4.1 Evolution of Ideas and Directions;88 10.4.2;3.4.2 What Went Wrong and What Went Right;88 10.4.3;3.4.3 Summary;89 10.5;References;89 11;Chapter 4. nML: A Structural Processor Modeling Language for Retargetable Compilation and ASIP Design;94 11.1;4.1 Introduction;94 11.2;4.2 The nML Processor Description Formalism;95 11.3;4.3 A Structural Skeleton of the Processor;95 11.3.1;4.3.1 Memories and Registers;96 11.3.2;4.3.2 Storage Aliases;97 11.3.3;4.3.3 Transitory Storage;97 11.3.4;4.3.4 Immediate Constants and Enumeration Types;98 11.3.5;4.3.5 Functional Units;99 11.4;4.4 Instruction-Set Grammar;99 11.4.1;4.4.1 Breaking Down the Instruction Set: AND Rules and OR Rules;101 11.4.2;4.4.2 The Grammar Attributes;102 11.4.3;4.4.3 Synthesized Attributes;102 11.4.4;4.4.4 Action Attribute;103 11.4.5;4.4.5 Image Attribute;106 11.4.6;4.4.6 Syntax Attribute;107 11.4.7;4.4.7 Mode Rules and Value Attributes;107 11.4.8;4.4.8 Inherited Attributes;109 11.5;4.5 Pipeline Hazards: Stalls and Bypasses;109 11.5.1;4.5.1 Control Hazards;110 11.5.2;4.5.2 Structural and Data Hazards;111 11.6;4.6 The Evolution of nML;114 11.7;4.7 A Retargetable Tool Suite for ASIPs;116 11.7.1;4.7.1 Chess: A Retargetable C Compiler;116 11.7.2;4.7.2 Checkers: A Retargetable Instruction-set Simulator Generator;117 11.7.3;4.7.3 Go: A Hardware Description Language Generator;117 11.7.4;4.7.4 Risk: A Retargetable Test-program Generator;117 11.7.5;4.7.5 Broad Architectural Scope;117 11.8;4.8 Design Examples;119 11.8.1;4.8.1 Portable Audio and Hearing Instruments;119 11.8.2;4.8.2 Wireline Modems;119 11.8.3;4.8.3 Wireless Modems;
120 11.8.4;4.8.4 Video Coding;120 11.8.5;4.8.5 Network Processing;120 11.9;4.9 Conclusions;121 11.10;References;121 12;Chapter 5. LISA: A Uniform ADL for Embedded Processor Modeling, Implementation, and Software Toolsuite Generation;124 12.1;5.1 Language-based ASIP Modeling;125 12.1.1;5.1.1 Intuitive Modeling Idea;125 12.1.2;5.1.2 ISA Modeling;125 12.1.3;5.1.3 Structure Modeling: Base Processor;128 12.1.4;5.1.4 Levels of Abstraction in LISA;129 12.1.5;5.1.5 LISA-based Processor Design;130 12.2;5.2 Automatic Software Toolsuite Generation;131 12.2.1;5.2.1 Instruction-set Simulator;132 12.2.2;5.2.2 The Compiler Designer;134 12.2.3;5.2.3 Custom Instruction Synthesis for LISA-based Processor Design;137 12.2.4;5.2.4 Instruction Opcode Synthesis;138 12.3;5.3 Automatic Optimized Processor Implementation;139 12.3.1;5.3.1 Automatic Generation of RTL Processor Description;139 12.3.2;5.3.2 Area and Timing-driven Optimizations;140 12.3.3;5.3.3 Energy-driven Optimizations;141 12.3.4;5.3.4 Automatic Generation of JTAG Interface and Debug Mechanism;142 12.4;5.4 Processor Verification;142 12.4.1;5.4.1 Equivalence Check via Simulation;143 12.4.2;5.4.2 Generation of Test Vectors from LISA Descriptions for Instruction-set Verification;144 12.5;5.5 System-Level Integration;146 12.5.1;5.5.1 Retargetable Processor Integration;147 12.5.2;5.5.2 Multiprocessor Simulation;148 12.6;5.6 Compact Modeling of Advanced Architectures;149 12.6.1;5.6.1 VLIW Architecture Modeling;150 12.6.2;5.6.2 Partially Reconfigurable Processor Modeling;151 12.7;5.7 Case Study;152 12.7.1;5.7.1 ASIP Development for Retinex-like Image and Video Processing;153 12.7.2;5.7.2 Retargetable Compiler Optimization for SIMD Instructions;156 12.8;5.8 Conclusions;159 12.9;References;159 13;Chapter 6. Expression: An ADL for Software Toolkit Generation, Exploration, and Validation of Programmable SOC Architectures;162 13.1;6.1 Expression ADL;163 13.1.1;6.1.1 Structure;164 13.1.2;6.1.2 Behavior;166 13.2;6.2 Software Toolkit Generat
ion and Exploration;168 13.2.1;6.2.1 Retargetable Compiler Generation;169 13.2.2;6.2.2 Retargetable Simulator Generation;171 13.2.3;6.2.3 Design Space Exploration;173 13.3;6.3 Architecture Synthesis for Rapid Prototyping;177 13.3.1;6.3.1 Synthesizable HDL Generation;177 13.3.2;6.3.2 Rapid Prototyping and Exploration;178 13.4;6.4 Functional Verification;180 13.4.1;6.4.1 Specification Validation;181 13.4.2;6.4.2 Test Generation Using Model Checking;182 13.4.3;6.4.3 Implementation Validation;185 13.5;6.5 Conclusions;187 13.6;References;188 14;Chapter 7. ASIP Meister;192 14.1;7.1 Overview of ASIP Meister;192 14.1.1;7.1.1 Framework Overview;193 14.1.2;7.1.2 Features;196 14.1.3;7.1.3 A Short History;197 14.1.4;7.1.4 ASIP Meister Usage in Academia;197 14.2;7.2 Architecture Model;197 14.3;7.3 ADL in ASIP Meister;199 14.3.1;7.3.1 Overview of ADL Structure;199 14.3.2;7.3.2 Specification Entry Using GUI;200 14.3.3;7.3.3 Microoperation Description;200 14.3.4;7.3.4 VLIW Extension;203 14.4;7.4 Generation of HDL Description;205 14.4.1;7.4.1 DFG Construction from Microoperation Description;206 14.4.2;7.4.2 Pipeline Registers and Datapath Selectors Insertion;206 14.5;7.5 Case Study;208 14.5.1;7.5.1 MIPS and DLX;208 14.5.2;7.5.2 M32R;209 14.5.3;7.5.3 MeP;209 14.6;7.6 Conclusion;210 14.7;7.7 Acknowledgments;210 14.8;References;211 15;Chapter 8. TIE: An ADL for Designing Application-specific Instruction Set Extensions;212 15.1;8.1 Introduction;212 15.1.1;8.1.1 Adapting the Processor to the Application;212 15.1.2;8.1.2 Tensilica Instruction Extension Language and Compiler;213 15.2;8.2 Design Methodology and Tools;213 15.2.1;8.2.1 Designing Application-specific Instructions;213 15.2.2;8.2.2 Design Automation with the TIE Compiler;215 15.3;8.3 Basics of Tie Language;216 15.3.1;8.3.1 A basic TIE Acceleration Example;216 15.3.2;8.3.2 Defining a Basic TIE Instruction;217 15.3.3;8.3.3 Instruction Encodings;218 15.3.4;8.3.4 Instruction Datapath;219 15.4;8.4 Adding Processor State;221 15.4.1;8.
4.1 Defining a State Register;221 15.4.2;8.4.2 Defining a Register File;223 15.4.3;8.4.3 Data Type and Compiler Support;225 15.4.4;8.4.4 Data Parallelism and SIMD;227 15.5;8.5 Vliw Machine Design;228 15.5.1;8.5.1 Defining a VLIW Instruction;229 15.5.2;8.5.2 Hardware Cost of VLIW;230 15.6;8.6 Language Constructs for Efficient Hardware Implementation;230 15.6.1;8.6.1 Sharing Hardware between Instructions;230 15.6.2;8.6.2 TIE Functions;231 15.6.3;8.6.3 Defining Multicycle Instructions;232 15.7;8.7 Custom Data Interfaces;234 15.7.1;8.7.1 Import Wire and Export State;235 15.7.2;8.7.2 TIE Queue;235 15.7.3;8.7.3 TIE Lookup;238 15.8;8.8 Hardware Verification;239 15.8.1;8.8.1 Microarchitectural Verification;240 15.9;8.9 Case Study of An Audio DSP Design;241 15.9.1;8.9.1 Architecture and ISA Overview;241 15.9.2;8.9.2 Implementation and Performance;242 15.10;8.10 Conclusions;243 15.11;References;244 16;Chapter 9. MADLAn ADL Based on a Formal and Flexible Concurrency Model;246 16.1;9.1 Introduction;246 16.2;9.2 Operation State Machine Model;247 16.2.1;9.2.1 Static OSM Model;248 16.2.2;9.2.2 Dynamic OSM Model;251 16.2.3;9.2.3 Scheduling of the OSM Model;253 16.3;9.3 MADL;255 16.3.1;9.3.1 The AND-OR Graph: A Review;256 16.3.2;9.3.2 The Core Layer;257 16.3.3;9.3.3 The Annotation Layer;260 16.4;9.4 Support for Tools;262 16.4.1;9.4.1 Cycle Accurate Simulator (CAS);262 16.4.2;9.4.2 Instruction Set Simulator;264 16.4.3;9.4.3 Disassembler;264 16.4.4;9.4.4 Register Allocator;264 16.4.5;9.4.5 Instruction Scheduler;266 16.5;9.5 Results;268 16.6;9.6 Related Work;271 16.7;9.7 Conclusion;273 16.8;References;273 17;Chapter 10. ADL++: Object-Oriented Specification of Complicated Instruction Sets and Microarchitectures;276 17.1;10.1 Flexible Architecture Simulation Toolset (FAST);277 17.1.1;10.1.1 Overview of the Toolset;277 17.2;10.2 The FAST/ADL Model;278 17.2.1;10.2.1 Timing of Events;280 17.2.2;10.2.2 Time Annotated Actions and Parallelism in the Microarchitecture;281 17.2.3;10.2.3 Microarc
hitecture Specification;282 17.2.4;10.2.4 ISA Specification;286 17.2.5;10.2.5 Putting It Together;288 17.3;10.3 Review of Complex Instruction Set Architectures;289 17.3.1;10.3.1 Variable Length Instructions;289 17.3.2;10.3.2 Many Memory Addressing Modes;290 17.3.3;10.3.3 Overlapping Registers;291 17.3.4;10.3.4 Mixed Arguments;292 17.3.5;10.3.5 Assembly Language Syntax;292 17.4;10.4 Sets and Regular Expressions as Language Constructs;293 17.4.1;10.4.1 Registers and Their Specification Using Sets;293 17.4.2;10.4.2 Regular Expressions and Addressing Modes;294 17.5;10.5 Instruction Templates and Multiple Conditional Inheritance;295 17.5.1;10.5.1 Inheritance with a Twist: Multiple Conditional Inheritance;296 17.5.2;10.5.2 Instruction Template;296 17.6;10.6 Object-Oriented Microarchitecture Specification;299 17.6.1;10.6.1 Artifacts as Objects;299 17.6.2;10.6.2 Deriving Complex Architectures From Objects;301 17.7;10.7 Epilogue;301 17.8;10.8 History of Fast and ADL++;301 17.9;References;302 18;Chapter 11. Processor Design with ArchC;304 18.1;11.1 Overview;304 18.2;11.2 Syntax and Semantics;305 18.3;11.3 Integration Through a TLM Interface;312 18.3.1;11.3.1 ArchC TLM Interfaces and Protocol;313 18.3.2;11.3.2 TLM Interrupt Port;314 18.3.3;11.3.3 A Word on ArchC Simulators;315 18.4;11.4 A Multicore Platform Example;317 18.5;11.5 Conclusions;322 18.6;References;322 19;Chapter 12. MAML: An ADL for Designing Single and Multiprocessor Architectures;324 19.1;12.1 History of MAML;325 19.2;12.2 Description of Single Processor Architectures;327 19.2.1;12.2.1 Syntax;327 19.2.2;12.2.2 Example of a VLIW Processor Architecture;334 19.3;12.3 Description of Multiprocessors;335 19.3.1;12.3.1 Related Work;336 19.3.2;12.3.2 Description of Parallel Processing Elements;337 19.3.3;12.3.3 Parametric Domains as a Description Paradigm;339 19.3.4;12.3.4 Description of Adaptive Interconnect Topologies;342 19.3.5;12.3.5 Case Study of a Tightly Coupled Processor Arrays;345 19.4;12.4 Approaches and Tools
Around MAML;346 19.4.1;12.4.1 Application Mapping;347 19.4.2;12.4.2 Design Framework;348 19.4.3;12.4.3 Interactive Visual Architecture Entry;349 19.4.4;12.4.4 Simulator Generation;350 19.4.5;12.4.5 Architecture Synthesis for Rapid Prototyping;353 19.5;12.5 Conclusions and Future Work;353 19.6;12.6 Acknowledgments;354 19.7;References;354 20;Chapter 13. GNR: A Formal Language for Specification, Compilation, and Synthesis of Custom Embedded Processors;358 20.1;13.1 Introduction;358 20.2;13.2 Overview of NISC Technology;361 20.3;13.3 Modeling NISC Architectures and Systems;364 20.3.1;13.3.1 GNR Formalism;366 20.3.2;13.3.2 GNR Rules;368 20.3.3;13.3.3 GNR Syntax;370 20.3.4;13.3.4 Basic Components;370 20.3.5;13.3.5 Hierarchical Components;371 20.3.6;13.3.6 Modeling an NISC Architecture;372 20.3.7;13.3.7 Communication Modeling;376 20.3.8;13.3.8 Generating RTL Code from GNR;380 20.4;13.4 Experiments: Design-Space Exploration Using NISC and GNR;382 20.4.1;13.4.1 Designing General-purpose NISCs;382 20.4.2;13.4.2 Custom Datapath Design for DCT;386 20.4.3;13.4.3 Communicating NISC Components;392 20.5;13.5 Conclusion;394 20.6;References;395 20.7;13.6 Index Terms;396 21;Chapter 14. HMDES, ISDL, and Other Contemporary ADLs;398 21.1;14.1 HMDES;398 21.1.1;14.1.1 HMDES Language;398 21.1.2;14.1.2 Structural Overview of Machine Description;402 21.1.3;14.1.3 Trimaran Infrastructure;412 21.2;14.2 ISDL;413 21.2.1;14.2.1 ISDL Language;414 21.2.2;14.2.2 ISDL-driven Methodologies;417 21.3;14.3 RADL;419 21.4;14.4 SIM-nML;419 21.5;14.5 UDL/I;421 21.6;14.6 Flexware;421 21.7;14.7 Valen-C;421 21.8;14.8 TDL;422 21.9;14.9 Conclusions;422 21.10;References;423 22;Index;424
