Multi-Threshold CMOS Digital Circuits Managing Leakage Power
discusses the Multi-threshold voltage CMOS (MTCMOS) technology, that has emerged as an increasingly popular technique to control the escalating leakage power, while maintaining high performance. The book addresses the leakage problem in a number of designs for combinational, sequential, dynamic, and current-steering logic. Moreover, computer-aided design methodologies for designing low-leakage integrated circuits are presented. The book give an excellent survey of state-of-the-art techniques presented in the literature as well as proposed designs that minimize leakage power, while achieving high-performance.
Multi-Threshold CMOS Digital Circuits Managing Leakage Power
is written for students of VLSI design as well as practicing circuit designers, system designers, CAD tool developers and researchers. It assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit design techniques.
Inhaltsverzeichnis
1. Introduction. - References. - 2. Leakage Power: Challenges and Solutions. - 2. 1 Introduction. - 2. 2 Power Dissipation in CMOS Digital Circuits. - 2. 3 Impact of Technology Scaling on Leakage Power. - 2. 4 (Vdd-Vth) Design Space. - 2. 5 Total Power Management. - 2. 6 Leakage Power Control Circuit Techniques. - 2. 7 Chapter Summary. - References. - 3. Embedded Mtcmos Combinational Circuits. - 3. 1 Introduction. - 3. 2 Basic Concept. - 3. 3 The Power Minimization Problem. - 3. 4 Algorithms. - 3. 5 Choosing the High-Vth Value. - 3. 6 Chapter Summary. - References. - 4. Mtcmos Combinational Circuits Using Sleep Transistors. - 4. 1 Introduction. - 4. 2 MTCMOS Design: Overview. - 4. 3 Variable Breakpoint Switch Level Simulator [1]. - 4. 4 Hierarchical Sizing Based on Mutually Exclusive Discharge Patterns. - 4. 5 Designing High-Vth Sleep Transistors, the Average Current Method [6]. - 4. 6 Drawbacks of Techniques. - 4. 7 Distributed Sleep Transistors [9] [10]. - 4. 8 Clustering Techniques. - 4. 9 Hybrid Heuristic Techniques. - 4. 10 Virtual Ground Bounce. - 4. 11 Results: Taking ground bounce into account. - 4. 12 Power Management of Sleep Transistors. - 4. 13 Chapter Summary. - References. - 5. Mtcmos Sequential Circuits. - 5. 1 Introduction. - 5. 2 MTCMOS Latch Circuit. - 5. 3 MTCMOS Balloon Circuit. - 5. 4 Intermittent Power Supply Scheme. - 5. 5 Auto-Backgate-Controlled MTCMOS. - 5. 6 Virtual Rails Clamp (VRC) Circuit. - 5. 7 Leakage Sneak Paths in MTCMOS Sequential Circuits. - 5. 8 Interfacing MTCMOS and CMOS blocks. - 5. 9 Impact of the High-Vth and Low-Vth values on MTCMOS Sequential Circuit Design. - 5. 10 Leakage Feedback Gates. - 5. 11 Chapter Summary. - References. - 6. Mtcmos Dynamic Circuits. - 6. 1 Introduction. - 6. 2 Clock-Delayed Domino Logic: Overview. - 6. 3 HS-Domino Logic. - 6. 4 MTCMOS CD-Domino Logic: Analysis and Overview. - 6. 5 MTCMOS HS-Domino (MHS-Domino) Logic. - 6. 6 Domino Dual Cascode Voltage Switch Logic (DDCVSL). - 6. 7 Chapter Summary. - References. - 7. Mtcmos Current-Steering Circuits. - 7. 1 MOS Current Mode Logic: Overview. - 7. 2 Introduction. - 7. 3 Minimum Supply Voltage: First Constraint. - 7. 4 Saturation Assurance: Second Constraint and the Proposed MTCMOS Design. - 7. 5 A 2. 5 Gbit/s 1:8 Demultiplexer in MTCMOS MCML. - 7. 6 Impact of Using MTCMOS Technology Over MCML Parameters. - 7. 7 Chapter Summary. - References.
