The Designer's Guide to VHDL

VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. The Designer's Guide to VHDL has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.

• First comprehensive book on VHDL to incorporate all new features of VHDL-2008, the latest release of the VHDL standard
• Helps readers get up to speed quickly with new features of the new standard
• Presents a structured guide to the modeling facilities offered by VHDL
• Shows how VHDL functions to help design digital systems
• Includes extensive case studies and source code used to develop testbenches and case study examples
• Helps readers gain maximum facility with VHDL for design of digital systems

1;Front Cover;1 2;The Designers Guide to VHDL;4 3;Copyright Page;5 4;Contents;8 5;Preface;18 6;Chapter 1. Fundamental Concepts;24 6.1;1.1 Modeling Digital Systems;24 6.2;1.2 Domains and Levels of Modeling;26 6.3;1.3 Modeling Languages;30 6.4;1.4 VHDL Modeling Concepts;30 6.5;1.5 Learning a New Language: Lexical Elements and Syntax;39 6.6;Exercises;52 7;Chapter 2. Scalar Data Types and Operations;54 7.1;2.1 Constants and Variables;54 7.2;2.2 Scalar Types;57 7.3;2.3 Type Classification;74 7.4;2.4 Attributes of Scalar Types;77 7.5;2.5 Expressions and Predefined Operations;80 7.6;Exercises;85 8;Chapter 3. Sequential Statements;88 8.1;3.1 If Statements;88 8.2;3.2 Case Statements;92 8.3;3.3 Null Statements;98 8.4;3.4 Loop Statements;99 8.5;3.5 Assertion and Report Statements;110 8.6;Exercises;116 9;Chapter 4. Composite Data Types and Operations;118 9.1;4.1 Arrays;118 9.2;4.2 Unconstrained Array Types;128 9.3;4.3 Array Operations and Referencing;137 9.4;4.4 Records;151 9.5;Exercises;157 10;Chapter 5. Basic Modeling Constructs;160 10.1;5.1 Entity Declarations and Architecture Bodies;160 10.2;5.2 Behavioral Descriptions;166 10.3;5.3 Structural Descriptions;199 10.4;5.4 Design Processing;209 10.5;Exercises;220 11;Chapter 6. Subprograms;230 11.1;6.1 Procedures;230 11.2;6.2 Procedure Parameters;236 11.3;6.3 Concurrent Procedure Call Statements;248 11.4;6.4 Functions;250 11.5;6.5 Overloading;256 11.6;6.6 Visibility of Declarations;259 11.7;Exercises;263 12;Chapter 7. Packages and Use Clauses;268 12.1;7.1 Package Declarations;268 12.2;7.2 Package Bodies;275 12.3;7.3 Use Clauses;280 12.4;Exercises;287 13;Chapter 8. Resolved Signals;290 13.1;8.1 Basic Resolved Signals;290 13.2;8.2 Resolved Signals, Ports, and Parameters;303 13.3;Exercises;310 14;Chapter 9. Predefined and Standard Packages;316 14.1;9.1 The Predefined Packages standard and env;316 14.2;9.2 IEEE Standard Packages;319 14.3;Exercises;358 15;Chapter 10 Case Study: A Pipelined Multiplier Accumulator;360 15.1;10.1 Algorith
m Outline;360 15.2;10.2 A Behavioral Model;363 15.3;10.3 A Register-Transfer-Level Model;369 15.4;Exercises;376 16;Chapter 11. Aliases;378 16.1;11.1 Aliases for Data Objects;378 16.2;11.2 Aliases for Non-Data Items;383 16.3;Exercises;386 17;Chapter 12. Generics;388 17.1;12.1 Generic Constants;388 17.2;12.2 Generic Types;395 17.3;12.3 Generic Lists in Packages;399 17.4;12.4 Generic Lists in Subprograms;412 17.5;12.5 Generic Subprograms;417 17.6;12.6 Generic Packages;430 17.7;Exercises;437 18;Chapter 13. Components and Configurations;440 18.1;13.1 Components;440 18.2;13.2 Configuring Component Instances;445 18.3;13.3 Configuration Specifications;460 18.4;Exercises;467 19;Chapter 14. Generate Statements;472 19.1;14.1 Generating Iterative Structures;472 19.2;14.2 Conditionally Generating Structures;478 19.3;14.3 Configuration of Generate Statements;488 19.4;Exercises;496 20;Chapter 15. Access Types;502 20.1;15.1 Access Types;502 20.2;15.2 Linked Data Structures;509 20.3;15.3 An Ordered-Dictionary ADT Using Access Types;514 20.4;Exercises;518 21;Chapter 16. Files and Input/Output;522 21.1;16.1 Files;522 21.2;16.2 The Package Textio;537 21.3;Exercises;553 22;Chapter 17. Case Study: A Package for Memories;558 22.1;17.1 The Memories Package;558 22.2;17.2 Using the Memories Package;569 22.3;Exercises;581 23;Chapter 18. Test Bench and Verification Features;582 23.1;18.1 External Names;582 23.2;18.2 Force and Release Assignments;593 23.3;18.3 Embedded PSL in VHDL;598 23.4;Exercises;605 24;Chapter 19. Shared Variables and Protected Types;608 24.1;19.1 Shared Variables and Mutual Exclusion;608 24.2;19.2 Uninstantiated Methods in Protected Types;620 24.3;Exercises;624 25;Chapter 20. Attributes and Groups;626 25.1;20.1 Predefined Attributes;626 25.2;20.2 User-Defined Attributes;639 25.3;20.3 Groups;651 25.4;Exercises;653 26;Chapter 21. Design for Synthesis;656 26.1;21.1 Synthesizable Subsets;656 26.2;21.2 Use of Data Types;657 26.3;21.3 Interpretation of Standard Logic Values;660
26.4;21.4 Modeling Combinational Logic;661 26.5;21.5 Modeling Sequential Logic;664 26.6;21.6 Modeling Memories;677 26.7;21.7 Synthesis Attributes;681 26.8;21.8 Metacomments;689 26.9;Exercises;690 27;Chapter 22. Case Study: System Design Using the Gumnut Core;692 27.1;22.1 Overview of the Gumnut;692 27.2;22.2 A Behavioral Model;704 27.3;22.3 A Register-Transfer-Level Model;727 27.4;22.4 A Digital Alarm Clock;744 27.5;Exercises;754 28;Chapter 23. Miscellaneous Topics;756 28.1;23.1 Guards and Blocks;756 28.2;23.2 IP Encryption;773 28.3;23.3 VHDL Procedural Interface (VHPI);793 28.4;23.4 Postponed Processes;799 28.5;23.5 Conversion Functions in Association Lists;802 28.6;23.6 Linkage Ports;808 28.7;Exercises;809 29;Appendix A: Standard Packages;816 29.1;A.1 The Predefined Package standard;816 29.2;A.2 The Predefined Package env;820 29.3;A.3 The Predefined Package textio;820 29.4;A.4 Standard VHDL Mathematical Packages;822 29.5;A.5 The std_logic_1164 Multivalue Logic System Package;825 29.6;A.6 Standard Integer Numeric Packages;829 29.7;A.7 Standard Fixed-Point Packages;839 29.8;A.8 Standard Floating-Point Packages;852 30;Appendix B: VHDL Syntax;864 30.1;B.1 Design File;866 30.2;B.2 Library Unit Declarations;866 30.3;B.3 Declarations and Specifications;868 30.4;B.4 Type Definitions;871 30.5;B.5 Concurrent Statements;873 30.6;B.6 Sequential Statements;875 30.7;B.7 Interfaces and Associations;878 30.8;B.8 Expressions and Names;879 31;Appendix C: Answers to Exercises;882 32;References;912 33;Index;914