This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.
- Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly
- Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence
- Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products
- Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes
Inhaltsverzeichnis
1;Front Cover;1 2;Electronic Design Automation: Synthesis, Verification, and Test;4 3;Copyright Page;5 4;Contents;6 5;Preface;22 6;In the Classroom;26 7;Acknowledgments;28 8;Contributors;30 9;About the Editors;34 10;CHAPTER 1 Introduction;38 10.1;1.1 Overview of electronic design automation;39 10.2;1.2 Logic design automation;50 10.3;1.3 Test automation;55 10.4;1.4 Physical design automation;62 10.5;1.5 Concluding remarks;69 10.6;1.6 Exercises;70 10.7;Acknowledgments;72 10.8;References;72 11;CHAPTER 2 Fundamentals of CMOS design;76 11.1;2.1 Introduction;76 11.2;2.2 Integrated circuit technology;77 11.3;2.3 CMOS logic;86 11.4;2.4 Integrated circuit design techniques;95 11.5;2.5 CMOS physical design;108 11.6;2.6 Low-power circuit design techniques;121 11.7;2.7 Concluding remarks;129 11.8;2.8 Exercises;129 11.9;Acknowledgments;132 11.10;References;132 12;CHAPTER 3 Design for testability;134 12.1;3.1 Introduction;135 12.2;3.2 Testability analysis;137 12.3;3.3 Scan design;146 12.4;3.4 Logic built-in self-test;155 12.5;3.5 Test Compression;176 12.6;3.6 Concluding remarks;198 12.7;3.7 Exercises;199 12.8;Acknowledgments;202 12.9;References;202 13;CHAPTER 4 Fundamentals of algorithms;210 13.1;4.1 Introduction;210 13.2;4.2 Computational complexity;212 13.3;4.3 Graph algorithms;222 13.4;4.4 Heuristic algorithms;245 13.5;4.5 Mathematical programming;258 13.6;4.6 Concluding remarks;267 13.7;4.7 Exercises;267 13.8;Acknowledgments;269 13.9;References;269 14;CHAPTER 5 Electronic system-level design and high-level synthesis;272 14.1;5.1 Introduction;273 14.2;5.2 Fundamentals of High-level synthesis;283 14.3;5.3 High-level synthesis algorithm overview;298 14.4;5.4 Scheduling;300 14.5;5.5 Register binding;310 14.6;5.6 Functional unit binding;318 14.7;5.7 Concluding remarks;326 14.8;5.8 Exercises;330 14.9;Acknowledgments;331 14.10;References;331 15;CHAPTER 6 Logic synthesis in a nutshell;336 15.1;6.1 Introduction;336 15.2;6.2 Data Structures for Boolean representation and reasoning;339
15.3;6.3 Combinational logic minimization;369 15.4;6.4 Technology mapping;399 15.5;6.5 Timing analysis;408 15.6;6.6 Timing optimization;421 15.7;6.7 Concluding remarks;429 15.8;6.8 Exercises;430 15.9;Acknowledgments;437 15.10;References;437 16;CHAPTER 7 Test synthesis;442 16.1;7.1 Introduction;443 16.2;7.2 Scan design;445 16.3;7.3 Logic built-in self-test (BIST) design.;462 16.4;7.4 RTL Design for testability;475 16.5;7.5 Concluding remarks;480 16.6;7.6 Exercises;480 16.7;Acknowledgments;483 16.8;References;483 17;CHAPTER 8 Logic and circuit simulation;486 17.1;8.1 Introduction;487 17.2;8.2 Logic simulation models;490 17.3;8.3 Logic simulation techniques;496 17.4;8.4 Hardware-accelerated logic simulation;502 17.5;8.5 Circuit simulation models;512 17.6;8.6 Numerical methods for transient analysis;517 17.7;8.7 Simulation of VLSI interconnects;522 17.8;8.8 Simulation of nonlinear devices;532 17.9;8.9 Concluding remarks;541 17.10;8.10 Exercises;543 17.11;Acknowledgments;546 17.12;References;547 18;CHAPTER 9 Functional verification;550 18.1;9.1 Introduction;551 18.2;9.2 Verification hierarchy;552 18.3;9.3 Measuring verification quality;557 18.4;9.4 Simulation-based approach;569 18.5;9.5 Formal approaches;577 18.6;9.6 Advanced research;598 18.7;9.7 Concluding remarks;600 18.8;9.8 Exercises;601 18.9;Acknowledgments;607 18.10;References;607 19;CHAPTER 10 Floorplanning;612 19.1;10.1 Introduction;612 19.2;10.2 Simulated annealing approach;617 19.3;10.3 Analytical approach;644 19.4;10.4 Modern floorplanning considerations;649 19.5;10.5 Concluding remarks;662 19.6;10.6 Exercises;662 19.7;Acknowledgments;668 19.8;References;668 20;CHAPTER 11 Placement;672 20.1;11.1 Introduction;672 20.2;11.2 Problem formulations;674 20.3;11.3 Global placement: partitioning-based approach;678 20.4;11.4 Global placement: simulated annealing approach;686 20.5;11.5 Global placement: analytical approach;690 20.6;11.6 Legalization;711 20.7;11.7 Detailed placement;712 20.8;11.8 Concluding Remarks;716
20.9;11.9 Exercises;717 20.10;Acknowledgments;719 20.11;References;719 21;CHAPTER 12 Global and detailed routing;724 21.1;12.1 Introduction;725 21.2;12.2 Problem definition;726 21.3;12.3 General-purpose routing;729 21.4;12.4 Global routing;734 21.5;12.5 Detailed Routing;741 21.6;12.6 Modern routing considerations;752 21.7;12.7 Concluding remarks;775 21.8;12.8 Exercises;777 21.9;Acknowledgments;782 21.10;References;782 22;CHAPTER 13 Synthesis of clock and power/ground networks;788 22.1;13.1 Introduction;788 22.2;13.2 Design considerations;790 22.3;13.3 Clock Network design;800 22.4;13.4 Power/ground network design;866 22.5;13.5 Concluding remarks;880 22.6;13.6 Exercises;880 22.7;Acknowledgments;883 22.8;References;883 23;CHAPTER 14 Fault Simulation and Test Generation;888 23.1;14.1 Introduction;888 23.2;14.2 Fault Collapsing;891 23.3;14.3 Fault Simulation;898 23.4;14.4 Test Generation;913 23.5;14.5 Advanced Test Generation;939 23.6;14.6 Concluding Remarks;946 23.7;14.7 Exercises;947 23.8;Acknowledgments;950 23.9;References;950 24;Index;956
