This book examines the issue of design of fully-integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discrete-time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior.
The book provides numerous real world applications, as well as practical rules-of-thumb for modern designers to use at the system, architectural, as well as the circuit level.
Inhaltsverzeichnis
Phase-Locked Loop Fundamentals. - Low-Voltage Analog Cmos Design. - Jitter Analysis in Phase-Locked Loops. - Low-Jitter PLL Architectures. - Digital PLL Design. - DSP Clock Generator Architectures. - Design for Testability in PLLs. - Clock Partitioning and Skew Control.
